1. Field of the Invention
The present invention relates to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a semiconductor device having a node contact structure of a complementary metal-oxide-semiconductor (CMOS) inverter.
2. Description of the Related Art
Static random access memory (SRAM) devices have advantages over many other semiconductor memory devices, with lower power consumption and higher operating speed. This is particularly true compared to dynamic random access memory (DRAM) devices. Therefore, SRAM has been widely used as a cache memory in computers and/or portable electronic appliances.
A unit cell of the SRAM device may be categorized as a load resistor SRAM cell or a CMOS SRAM cell. The load resistor SRAM cell typically employs a high load resistor as a load device, while the CMOS SRAM cell typically employs a p-channel metal-oxide-semiconductor (PMOS) transistor as a load device.
CMOS SRAM cells may be classified into two types. One type of CMOS SRAM cell is a thin film transistor (TFT) SRAM cell, which may employ TFT's stacked on a semiconductor substrate as the load device. Another type is a bulk CMOS SRAM cell, which may employ bulk transistors formed at a semiconductor substrate as the load device.
The bulk CMOS SRAM cell may exhibit higher cell stability as compared to the TFT SRAM cell and the load resistor SRAM cell. In other words, the bulk CMOS SRAM cell may have excellent low voltage characteristics and low stand-by current. This is because all of the transistors constituting the bulk CMOS SRAM cell are formed at a single crystalline semiconductor substrate. In contrast, the TFTs of the TFT SRAM cells are typically formed using a polysilicon layer as a body layer. However, the bulk CMOS SRAM cell may have lower integration density as well as weaker latch-up immunity as compared to the TFT SRAM cell. Therefore, to produce a highly integrated SRAM device having high reliability, the characteristics of the load transistors employed in the TFT SRAM cell may need to be improved.
In addition, each of the SRAM cells has a pair of node contact structures. In particular, each of the node contact structures of the TFT SRAM cell is a contact structure, which electrically connects a P-type drain region of the load transistor to an N-type drain region of a driver transistor. In this case, there is a need for an ohmic contact between the P-type drain region of the load transistor and the N-type drain region of the driver transistor.
Semiconductor devices having TFTs stacked on a semiconductor substrate are described in U.S. Pat. No. 6,022,766 to Chen, et al., entitled “Semiconductor Structure Incorporating Thin Film Transistors and Methods for Its Manufacture.” According to Chen, et al., a typical bulk transistor is formed at a single crystalline silicon substrate, and a TFT is formed over the bulk transistor. Either the source or the drain region of the bulk transistor is electrically connected to the source or drain region of the TFT through a metal plug such as a tungsten plug. Therefore, even though the bulk transistor and the TFT are an NMOS transistor and a PMOS transistor, respectively, the bulk transistor has an ohmic contact with respect to the TFT through the metal plug.
A body layer of the TFT may be formed by depositing an amorphous silicon layer on the semiconductor substrate having the metal plug, and crystallizing the amorphous silicon layer using a thermal treatment process. In this case, the body layer may be a polysilicon layer having large grains. As such, it may be difficult to convert the body layer into a perfect single crystalline silicon layer. As a result, it may be difficult to form TFTs having electrical characteristics comparable to that of the bulk transistor. Accordingly, there is a need for techniques for enhancing characteristics of the TFT stacked over a semiconductor substrate.
Further, a method of converting the body layer into a single crystalline semiconductor layer using a solid phase epitaxial process is disclosed in U.S. Pat. No. 5,156,987 to Sandhu, et al., entitled “High Performance Thin Film Transistor by Solid Phase Epitaxial Regrowth.” According to Sandhu, et al., the body layer in which a channel region and source/drain regions of the TFT are formed is crystallized using a drain region of a bulk transistor formed at a semiconductor substrate as a seed layer. That is, the body layer is formed to directly contact the drain region of the bulk transistor, and the body layer is crystallized using the solid phase epitaxial process. In this case, if the bulk transistor is a NMOS transistor and the TFT is a PMOS transistor, there is a need to enhance a contact resistance characteristic between the drain regions of the bulk transistor and the TFT.